The present invention relates to a semiconductor circuit device and, more particularly, to a semiconductor circuit device which can prevent an output of a bistable circuit from becoming unstable.
A bistable circuit has two output stable states. FIG. 1 shows an example of such a bistable circuit. This bistable circuit is an R-S flip-flop circuit comprising: a latch section consisting of two inverters I1 and I2; and N type MOS transistors Q1 and Q2 in which a set signal and a reset signal are supplied to each gate.
FIG. 2 shows the operation characteristics of this flip-flop circuit. In this diagram, curve L1 indicates input and output characteristics of inverter I1 in the case where a Q output terminal is regarded as an input and a Q output terminal is regarded as an output. Curve L2 represents input and output characteristics of inverter I2 in the case where the Q output terminal is regarded as an input and the Q output terminal is regarded as an output. Each of cross points A, B, and C of curves L1 and L2 is a stable point of this flip-flop. At cross point A, the Q output terminal is set to the logic "0" level and the Q output terminal is set to the "1" level. At cross point C, the Q output terminal is set to the logic "1" level and the Q output terminal is set to the "0" level. At cross point B, both of the Q and Q output terminals are in a logically unstable state, i.e., they are set to the intermediate potential between the logics "0" and "1". This potential is almost equal to a threshold voltage value of the circuit.
Therefore, when the reset signal is at the "0" level, and the set signal of the "1" level as shown in FIG. 3A is supplied to a gate of transistor Q1, the potential of the Q output terminal is set to the "1" level as shown in FIG. 3B. However, if the potential of a level lower than the "1" level as shown in, e.g., FIG. 3C or 3E was supplied to the gate of transistor Q1 due to the influence of noise and the like, the potential of the Q output terminal may be set to a logically unstable state as shown in FIG. 3D or 3F.
If the potential of the Q output terminal became logically unstable due to the influence of noise and the like, an unexpected fluctuation in the circuit, which is provided at the next stage would occur. Causing the circuit to malfunction.